An Introduction of the CD4069UBE CMOS Inverter


The CD4069UBE comprises CMOS inverter circuits. It is designed for all general-purpose inverter systems. It comes with standard symmetrical output features. It meets the specifications in JEDEC preliminary standard No. 13B. It is general use and is suitable for logic inversion, pulse shaping, oscillators, and as well as high-input-impedance amplifiers.


Medium speed operation: tPHL, tPLH = 30ns at 10 V

100% tested for quiescent current at 20 V

The maximum input current of 1 µA at 18 V over full package-temperature range, 100nA at 18V and 25°C



CAD Model




PCB Footprints

PCB Footprints

3D Models

3D Models


Supply Chain

Factory Lead Time – 6 Weeks


Package / Case – 14-DIP (0.300, 7.62mm)

Weight – 927.99329mg


Operating Temperature –   -55°C~125°C

Circuits of CD4069UBE

Circuits of TL431CZ

Alternative Models

MC14049UBCPG, CD4502BE, CD4009UBE

Where to Use CD4069UBE?

The CD4069UBE CMOS inverter has the benefit of a complementary structure. It is now one of the most popular devices used in digital circuit design. The CMOS inverter is a complement push-pull device made up of P-MOSFET as well as N-MOSFET. N-MOSFET is the driver tube. P-MOSFET is for load tube. The gate of the two transistors is connected to form signals input. The two transistors are connected separately to the source. The N-MOSFET’s origin is located in the ground. The p-MOSFET’s source voltage is connected to the voltage of the supply. The n-MOSFET connects to the P-MOSFET’s drain as an output from the inverter. To manufacture P-MOSFETs and n-MOSFETs in integrated circuits, they must create an insulated P-substrate as well as an n-substrate zone. The CD4069UBE CMOS inverter circuits for CMOS may include other circuits ancillary to it like electrostatic discharge protection circuits as well as latch protection circuits as well as input shaping circuits for Schmidt.

 CMOS inverter

How to Use CD4069UBE?

The CD4069UBE CMOS inverter circuit is made up of two MOSFETs with enhanced performance. V1 refers to the NMOS Tube which is also known as the drive tube. V2 is a PMOS tube which is a load tube. The voltage of the gate’s source UTN in the NMOS tube is high. Its gate-source source’s opening voltage PMOS tube is negative. Its range of values is 2 to 5 V. To allow the circuit to function correctly it is necessary to supply the voltage UDD>(UTN+|UTP|)is needed. The UDD is able to operate from 3 to 18V. It is able to operate in a wider scope of applications.

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